package miggy.cpu.instructions.bchg;

import miggy.cpu.*;
import miggy.api.cpu.*;
import miggy.cpu.operands.OperandFactory;
import miggy.SystemModel;

/*
//  Miggy - Java Amiga MachineCore
//  Copyright (c) 2008, Tony Headford
//  All rights reserved.
//
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
//  following conditions are met:
//
//    o  Redistributions of source code must retain the above copyright notice, this list of conditions and the
//       following disclaimer.
//    o  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
//       following disclaimer in the documentation and/or other materials provided with the distribution.
//    o  Neither the name of the Miggy Project nor the names of its contributors may be used to endorse or promote
//       products derived from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
//  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
//  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
//  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// $Revision: 21 $
*/
public class BCHG_dyn implements Instruction
{
	public final void register(InstructionSet set)
	{
		int base = 0x0140;
		for(int r = 0; r < 8; r++)
		{
			for(int mode = 0; mode < 8; mode++)
			{
				if(mode == 1)
					continue;
				for(int reg = 0; reg < 8; reg++)
				{
					if(mode == 7 && reg > 1)
						break;

					set.add(base + (r << 9) + (mode << 3) + reg, this);
				}
			}
		}
	}

	public int execute(int opcode)
	{
		int bit = 1 << (SystemModel.CPU.getDataRegister((opcode & 0x0e00) >> 9));
		Operand dst = OperandFactory.fetchOperand((opcode & 0x0038) >> 3, (opcode & 0x007), false, Size.Long);
		int time;

		Size size;
		int dstv;
		//only a long op if Dest is DataReg
		if(dst.isRegister())
		{
			size = Size.Long;
			dstv = dst.get(size);
			time = 8;
		}
		else
		{
			size = Size.Byte;
			dstv = dst.get(size);
			time = 8 + dst.timing(size);
		}

		if((dstv & bit) == 0)
		{
			//not originally set so set Z flag
			SystemModel.CPU.setFlag(CpuFlag.Z);
			// set the bit
			dstv |= bit;
		}
		else
		{
			//originally set so clr Z flag
			SystemModel.CPU.clrFlag(CpuFlag.Z);
			// clr the bit
			dstv &= (~bit);
		}
		dst.put(dstv, size);
		return time;
	}

	public DecodedInstruction disassemble(int address, int opcode)
	{
		Size size = Size.Long;
		DecodedInstructionImpl di = new DecodedInstructionImpl("bchg", opcode, address, size);
		//immediate src value
		di.setSrc(OperandFactory.dataReg((opcode & 0x0e00) >> 9));
		di.setDst(OperandFactory.valueOf(address + 2, (opcode & 0x0038) >> 3, (opcode & 0x007), false, size));
		return di;
	}
}
